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 l l
Logic-Level Gate Drive Advanced Process Technology l Surface Mount (IRLZ34NS) l Low-profile through-hole (IRLZ34NL) l 175C Operating Temperature l Fast Switching l Fully Avalanche Rated l Lead-Free Description
HEXFET Power MOSFET
D
IRLZ34NSPbF IRLZ34NLPBF (R)
VDSS = 55V RDS(on) = 0.035
PD - 95583
G
ID = 30A
S
Absolute Maximum Ratings
ID @ TC = 25C ID @ TC = 100C IDM PD @TA = 25C PD @TC = 25C V GS EAS IAR EAR dv/dt TJ TSTG
Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The D2Pak is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible onresistance in any existing surface mount package. The D2Pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application. The through-hole version (IRLZ34NL) is available for lowprofile applications.
D 2 Pak
TO-262
Parameter
Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds
Max.
30 21 110 3.8 68 0.45 16 110 16 6.8 5.0 -55 to + 175 300 (1.6mm from case )
Units
A W W W/C V mJ A mJ V/ns C
Thermal Resistance
Parameter
RJC RJA Junction-to-Case Junction-to-Ambient ( PCB Mounted,steady-state)**
Typ.

Max.
2.2 40
Units
C/W
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1
07/20/04
IRLZ34NS/LPbF
Electrical Characteristics @ TJ = 25C (unless otherwise specified)
Parameter Drain-to-Source Breakdown Voltage V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient V (BR)DSS RDS(on) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LS Ciss Coss Crss Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time Min. 55 1.0 11 Typ. 0.065 8.9 100 21 29 Max. Units Conditions V V GS = 0V, ID = 250A V/C Reference to 25C, ID = 1mA 0.035 V GS = 10V, ID = 16A 0.046 V GS = 5.0V, ID = 16A 0.060 V GS = 4.0V, ID = 14A 2.0 V V DS = V GS, ID = 250A S V DS = 25V, I D = 16A 25 V DS = 55V, V GS = 0V A 250 V DS = 44V, VGS = 0V, TJ = 150C 100 V GS = 16V nA -100 V GS = -16V 25 I D = 16A 5.2 nC V DS = 44V 14 V GS = 5.0V, See Fig. 6 and 13 V DD = 28V I D = 16A ns R G = 6.5, V GS = 5.0V R D = 1.8, See Fig. 10 Between lead, 7.5 nH and center of die contact 880 V GS = 0V 220 pF V DS = 25V 94 = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
Min. Typ. Max. Units IS
I SM
V SD trr Q rr ton
Conditions D MOSFET symbol 30 showing the A G integral reverse 110 S p-n junction diode. 1.3 V TJ = 25C, IS = 16A, VGS = 0V 76 110 ns TJ = 25C, IF = 16A 190 290 nC di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 ) RG = 25, IAS = 16A. (See Figure 12)
ISD 16A, di/dt 270A/s, VDD V(BR)DSS,
TJ 175C
VDD = 25V, starting TJ = 25C, L =610H
Pulse width 300s; duty cycle 2%. Uses IRLZ34N data and test conditions
** When mounted on 1" square PCB ( FR-4 or G-10 Material ). For recommended footprint and soldering techniques refer to application note #AN-994.
2
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IRLZ34NS/LPbF
1000
VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V TOP
1000
ID , Drain-to-Source Current (A)
100
ID , Drain-to-Source Current (A)
100
VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V TOP
10
10
2.5V
1
1
2.5V
0.1 0.1
20s PULSE WIDTH T J = 25C
1 10
A
100
0.1 0.1
20s PULSE WIDTH T J = 175C
1 10
A
100
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
R DS(on) , Drain-to-Source On Resistance (Normalized)
1000
3.0
I D = 27A
I D , Drain-to-Source Current (A)
2.5
100
TJ = 25C TJ = 175C
10
2.0
1.5
1.0
1
0.5
0.1 2 3 4 5 6
V DS = 25V 20s PULSE WIDTH
7 8 9 10
A
0.0 -60 -40 -20 0 20 40 60
VGS = 10V
80 100 120 140 160 180
A
VGS , Gate-to-Source Voltage (V)
TJ , Junction Temperature (C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
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3
IRLZ34NS/LPbF
1400
V GS , Gate-to-Source Voltage (V)
1200
V GS = 0V, f = 1MHz C iss = Cgs + C gd , Cds SHORTED C rss = C gd Ciss C oss = C ds + C gd
15
I D = 16A V DS = 44V V DS = 28V
12
C, Capacitance (pF)
1000
800
9
Coss
600
6
400
Crss
200
3
0 1 10 100
A
0 0 4 8 12 16
FOR TEST CIRCUIT SEE FIGURE 13
20 24 28 32
A
VDS , Drain-to-Source Voltage (V)
Q G , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
1000
1000
ISD , Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED BY R DS(on)
100
I D , Drain Current (A)
100 10s
TJ = 175C TJ = 25C
10
100s 10 1ms
1 0.4 0.6 0.8 1.0 1.2 1.4 1.6
VGS = 0V
1.8
A
1 1
TC = 25C TJ = 175C Single Pulse
10
10ms
2.0
A
100
VSD , Source-to-Drain Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRLZ34NS/LPbF
40
V DS V GS
RD
ID , Drain Current (A)
30
RG 5.0V
D.U.T.
+
V DD -
20
Pulse Width 1 s Duty Factor 0.1 %
Fig 10a. Switching Time Test Circuit
10
VDS 90%
0 25 50 75 100 125 150 175
TC , Case Temperature ( C)
Fig 9. Maximum Drain Current Vs. Case Temperature
10% VGS
td(on) tr t d(off) tf
Fig 10b. Switching Time Waveforms
10
Thermal Response (Z thJC )
1
D = 0.50 0.20 0.10 0.05 PDM SINGLE PULSE (THERMAL RESPONSE) t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.0001 0.001 0.01 0.1
0.1
0.02 0.01
0.01 0.00001
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRLZ34NS/LPbF
L VDS D.U.T. RG + V - DD
5.0 V
EAS , Single Pulse Avalanche Energy (mJ)
250
TOP
200
BOTTOM
ID 6.6A 11A 16A
IAS tp
0.01
150
100
Fig 12a. Unclamped Inductive Test Circuit
50
V(BR)DSS tp VDD VDS
0
VDD = 25V
25 50 75 100 125 150
A
175
Starting TJ , Junction Temperature (C)
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
IAS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator Same Type as D.U.T.
50K
QG
12V
.2F .3F
5.0 V
QGS VG QGD
VGS
3mA
D.U.T.
+ V - DS
Charge
IG
ID
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform
Fig 13b. Gate Charge Test Circuit
6
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IRLZ34NS/LPbF
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
-
+
RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
+ V DD
Driver Gate Drive P.W. Period D=
P.W. Period VGS=10V
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
VDD
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS
= 5V for Logic Level Devices
Fig 14. For N-Channel HEXFETS
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7
IRLZ34NS/LPbF
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
D2Pak Part Marking Information
T H IS IS AN IR F 530S WIT H L OT CODE 8024 AS S E MB L E D ON WW 02, 2000 IN T HE AS S E MB L Y L INE "L " Note: "P" in as s embly line pos ition indicates "L ead-F ree" INT E R NAT IONAL R E CT IF IE R L OGO AS S E MB L Y L OT CODE PAR T NU MB E R F 530S DAT E CODE YE AR 0 = 2000 WE E K 02 L INE L
OR
INT E R NAT IONAL RE CT IF IE R L OGO AS S E MB LY L OT CODE P ART NU MB E R F 530S DAT E CODE P = DE S IGNAT E S L E AD-F RE E P RODU CT (OP T IONAL ) YE AR 0 = 2000 WE E K 02 A = AS S E MB L Y S IT E CODE
8
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IRLZ34NS/LPbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
E XAMPL E: T HIS IS AN IRL 3103L L OT CODE 1789 AS S EMBL ED ON WW 19, 1997 IN T HE AS S E MB LY LINE "C" Note: "P" in ass embly line pos ition indicates "Lead-Free" INT ERNAT IONAL RE CT IFIER LOGO AS S E MBL Y LOT CODE PART NUMBER
DAT E CODE YE AR 7 = 1997 WE EK 19 LINE C
OR
INTE RNAT IONAL RECT IF IER LOGO AS S EMBLY L OT CODE PART NUMB ER DATE CODE P = DE S IGNAT E S L EAD-FREE PRODUCT (OPTIONAL) YEAR 7 = 1997 WEE K 19 A = AS S EMBL Y S IT E CODE
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9
IRLZ34NS/LPbF
D2Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153)
1.60 (.063) 1.50 (.059) 0.368 (.0145) 0.342 (.0135)
FEED DIRECTION 1.85 (.073)
1.65 (.065)
11.60 (.457) 11.40 (.449)
15.42 (.609) 15.22 (.601)
24.30 (.957) 23.90 (.941)
TRL
10.90 (.429) 10.70 (.421) 1.75 (.069) 1.25 (.049) 16.10 (.634) 15.90 (.626) 4.72 (.136) 4.52 (.178)
FEED DIRECTION
13.50 (.532) 12.80 (.504)
27.40 (1.079) 23.90 (.941)
4
330.00 (14.173) MAX.
60.00 (2.362) MIN.
NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039) 24.40 (.961) 3
30.40 (1.197) MAX. 4
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 07/04
10
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Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/


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